Gates / DTL / ChipGate

ChipGate

Open source

Structural sanity checker for Verilog RTL. Finds undriven outputs, multi-driven signals and unintended latches.

View the repository Open the lab

What it checks

Undriven and multi-driven signals
Unintended latch inference
Structural design-rule violations

What it does not check

It is not formal verification, not timing sign-off and not a replacement for your EDA toolchain.

Where it sits

ChipGate runs inside DTL

DTL

Deterministic Taxonomy Lanes

Is this output or decision allowed?

DTL routes an output or decision into a defined verification lane, applies machine-readable rules, and returns a categorical result with the reasoning recorded. It does not score confidence. It decides, or it declines to decide.

acceptblockreviewabstainpending evidence

Evidence

Every verdict leaves a record

Property	Behaviour
Determinism	The same input produces the same verdict. A result that does not reproduce is treated as a defect.
Signing	Verdicts are Ed25519 signed and anchored in a tamper-evident chain.
Replay	A sealed pack can be re-run later to detect verification drift.
Availability	Fail-closed. If this gate cannot be reached, the result is recorded as unavailable, never as a pass.
Independence	A third party can verify a pack without our source code and without contacting us.